The present invention relates generally to integrated circuit memory devices and, more particularly, to improving write time for Dynamic Random Access Memories (DRAMs) having a destructive read architecture.
The evolution of sub-micron CMOS technology has resulted in significant improvement in microprocessor speeds. Quadrupling roughly every three years, microprocessor speeds have now even exceeded 1 Ghz. Along with these advances in microprocessor technology have come more advanced software and multimedia applications, requiring larger memories for the application thereof. Accordingly, there is an increasing demand for larger Dynamic Random Access Memories (DRAMs) with higher density, speed and performance.
One of the longest delays associated with the operation of a DRAM is the write time thereto. An individual DRAM cell, having a transistor and a capacitor as its core components, also has internal resistance and parasitic capacitances as a result of the metallic and dielectric material used in the fabrication thereof. In turn, the internal resistance and parasitic capacitances cause an RC time delay when the cell voltage is changed from one logic state to the other logic state. This is particularly the case where a DRAM cell initially has a xe2x80x9clogic 0xe2x80x9d bit stored therein (e.g., the cell voltage is at 0 volts or ground), and it is thereafter desired to write a xe2x80x9clogic 1xe2x80x9d to the cell (e.g., increasing the cell voltage to a selected supply voltage value VDD).
Because a write operation is often performed sequentially with other operations (e.g., a read operation) in a conventional DRAM architecture, the overall delay in completing an entire DRAM operation can become problematic.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for preparing a dynamic random access memory (DRAM) cell for a write operation, thereby creating a preset condition prior to a write back operation in a destructive read architecture. In an exemplary embodiment, the method includes creating a preset voltage level within the cell, which preset voltage level has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when the cell has a 0 bit stored therein, and the logic 1 voltage level corresponds to a second cell voltage value when the cell has a 1 bit stored therein. Prior to the creation of the preset voltage level within the cell, the cell has an initial voltage value corresponding to either the logic 0 voltage level or the logic 1 voltage level.
In one embodiment, the preset voltage level is about halfway between the logic 1 voltage level and the logic 0 voltage level. The preset voltage level is greater than half the difference between the logic 1 voltage level and the logic 0 voltage level if the initial voltage value of the cell corresponds to the logic 1 voltage level. However, the preset voltage level is less than half the difference between the logic 1 voltage level and the logic 0 voltage level if the initial voltage value of the cell corresponds to said logic 0 voltage level. In an alternative embodiment, the preset voltage level is at least xc2xe of the logic 1 voltage level.